1. Field of the Invention
The present invention relates to a filter and, more particularly, to a tuning circuit of a filter for correcting a cut-off frequency of the filter.
2. Description of the Related Art
FIG. 1a shows a related art tuning circuit.
The tuning circuit as shown in FIG. 1a is disclosed in a U.S. Patent Laid Open Publication No. US 2004/0169565.
As shown in FIG. 1a, the tuning circuit comprises a filter unit 110, a comparator 120, and a controller unit 130.
The filter unit 110 comprises a first RC unit 111a, a second RC unit 111b, switches SW1a, SW1b, SW2a, and SW2b for charging and discharging the first and second RC units 111a and 111b, and a capacitor array 112 for controlling capacitance values of the first and second RC units 111a and 111b. 
The comparator 120 compares two inputs ({circle around (1)} and {circle around (2)}), and the controller unit 130 comprises a sequence controller 131 and a memory 132.
Herein, when a start signal is inputted to the sequence controller 131, the first and third switches SW1a and SW1b are turned on (close) according to a control signal (A) of an output terminal of the sequence controller 131. When a stop signal is inputted to the sequence controller 131, the second and fourth switches SW2a and SW2b are turned off (open) according to a control signal (B) of the output terminal of the sequence controller 131.
Although not shown, in order to perform a tuning operation, first, the first and third switches SW1a and SW1b should be turned on (close) and the second and fourth switches SW2a and SW2b should be turned off (open), so that the first capacitor (C1a) can be in a discharged state and the second capacitor (C1b) can be in a charged state.
After the proceeding process, when an input terminal start control signal of the sequence controller 131 is applied, the first and third switches SW1a and SW1b are turned off (open) and the second and fourth switches SW2a and SW2b are turned on (close), so that the first capacitor C1a is connected with a first resister R1a and gradually charged as time goes by and the second capacitor C1b is connected with a second resister R1b and gradually discharged as time goes by.
As the above process is performed, the comparator 120 compares a value of the first node ({circle around (1)}) of the first RC unit 111a and the second node ({circle around (2)}) of the second RC unit 111b. 
Herein, upon comparing the values of the first and second nodes ({circle around (1)} and {circle around (2)}), namely, the inputs to the comparator 120, if the output voltages of the first and second RC units 111a and 111b are reversed compared with an initial comparison state, the comparator 120 outputs a stop signal and the sequence controller 131 checks a corresponding time point and stores a clock time of a digital counter in the memory 132.
Resultantly, the first RC unit 111a has a first time constant (t1) and the second RC unit 111b has a second time constant (t2), and in this respect, the first and second capacitors C1a and C1b are controlled by the capacitor array 112 so that the first and second time constants t1 and t2 can become the same.
FIG. 1b is a graph for explaining the tuning operation of the related art tuning circuit. With reference to in FIG. 1b, as mentioned above with reference to FIG. 1a, the control signal (A) for starting tuning is turned off (open) and the control signal (B) is turned on (close), so that, at the start time point (tstart), the first RC unit starts to be charged while the second RC unit starts to be discharged.
Namely, the first time constant (t1) of the first RC unit is R1*C1 and the second time constant (t2) of the second RC unit is R2*C2.
As illustrated, time points at which the first and second RC units have the same charging and discharging change from Δt1 to Δt2 or to Δt3 at intersection nodes S1, S2, and S3 according to a device.
However, the related art method has the following problems. That is, because it does not use an external absolute reference that is not related to a change in PVT (Process, Voltage and Temperature), the tuned intersection nodes can be changed according to a change in the PVT.
In addition, since matching is performed according to a change in the first and second RC units, resultantly, tuning is made only at the intersection nodes S1, S2 or S3, so the tuning range is very narrow depending on a chip and every chip needs a tuning simulation.